1. Field of the Invention
The present invention relates in general to a method of forming a contact structure in particular, the present invention relates to a method of forming a bit line contact structure comprising an inner landing pad and a contact plug.
2. Description of the Related Art
Embedded DRAM applications demand both the utmost in high-performance CMOS (complementary metal oxide semiconductor) logic devices and high-density DRAM arrays. High-performance CMOS logic devices require low-resistance gate conductors and source drain diffusions (salicidation), which drive processes that are costly and difficult to integrate with high-density DRAM processes. For example, salicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bit line contact plugs which are borderless to adjacent word line conductors; also, salicided junctions in the array may result in increased current leakage of the memory device.
In a typical DRAM array, the word lines need to be capped with an insulator, while in the supports the gate conductors must be exposed to allow the introduction of the dual work functions doping and salicidation. Conventional solutions to these integration problems require additional masking steps to remove the insulating gate cap from the support MOSFETs prior to the salicidation process.
In the conventional method, the contact plugs in the memory array region and the logic circuit region are performed individually. Usually, the contact plug process of the memory array region occurs before the contact plug process of the logic circuit region. A BPSG layer and a TEOS layer cover the transistors and then the stacked layer is etched to form bit line contact holes (referred to as CB holes) in the memory array region. The polysilicon material is then filled into the bit line contact holes to form bit line contact plugs. The contact plug process of the logic circuit region is performed to form gate electrode contact holes (referred to as CG holes) and junction contact holes (referred to as CS holes) in the stacked BPSG/TEOS layer in the logic circuit region. An M0 etching process is performed to define the M0 landing pad of the bit line contact plugs and the local interconnection between the gate electrode contact plug and the junction contact plug in the logic circuit region.
During formation of the bit line contact plugs, etching through the stacked TEOS /BPSG layer is necessary. However, this may cause loss of silicon atoms in the substrate, resulting in serious sub-threshold voltage and damage to the memory ability of the capacitors. The gaps between gate electrodes may be too small to etch and form the bit line contact holes, resulting in open circuits. Moreover, the spacers protecting the gate electrodes may be lost during etching, resulting in open circuits.
To solve the above mentioned problems, an object of the present invention is to provide a method of forming a bit line contact plug to prevent the loss of silicon atoms in the substrate during the etching process.
It is another object of the present invention to provide a method of forming a bit line contact plug to resolve the issue of the gaps between gate electrodes being too small to etch and form the bit line contact plugs.
It is still another object of the present invention to provide a method of forming a bit line contact plug to resolve the issue of the short circuit between the adjacent bit lines.
The present invention provides a method of forming a bit line contact structure, comprising: providing a substrate with a transistor including a gate electrode and a source/drain region thereon, the gate electrode being protected with a first insulating layer; conformally forming a titanium layer on the substrate with the transistor thereon; conformally forming a titanium nitride layer on the titanium layer; conformally forming a tungsten layer on the titanium nitride layer; defining the tungsten layer, the titanium nitride layer and the titanium layer to form an inner landing pad on the source/drain region; conformally forming a passivation layer on the inner landing pad, the transistor and the substrate; forming a second insulating layer with a even surface on the passivation layer; forming a hole in the second insulating layer and the passivation layer to expose the inner landing pad; and filling a metal material in the contact hole.
The present invention also provides a method of forming a bit line contact structure on a substrate having a memory array region and a logic circuit region and having a transistor including a gate electrode and a source/drain region thereon, the gate electrode being protected with an first insulating layer, the method comprising: conformally forming a titanium layer on the substrate with the transistor thereon; conformally forming a titanium nitride layer on the titanium layer; conformally forming a tungsten layer on the titanium nitride layer; defining the tungsten layer, the titanium nitride layer and the titanium layer to form an inner landing pad in the memory array region to contact the source/drain region; conformally forming a passivation layer on the inner landing pad, the transistor and the substrate; forming a second insulating layer with a even surface on the passivation layer; forming first, second and third contact holes in the second insulating layer and the passivation layer to expose the inner landing pad in the memory array region, the gate electrode in the logic circuit region and the source/drain region in the logic circuit region respectively; and filling a metal material in the first, second and third contact holes.
The present invention also provides a bit line contact structure, comprising: a substrate; a transistor on the substrate, the transistor including a gate electrode and a source/drain region, the gate electrode protected with a first insulating layer; an inner landing pad on a surface of the transistor and the source/drain region, the inner landing pad comprising a conformal tungsten/titanium nitride /titanium stacked layer from up to bottom; a passivation layer on the inner landing pad, the transistor and the substrate; a second insulating layer with a even surface on the passivation layer; a contact plug in the second insulating layer and the passivation layer to contact the inner landing pad; and an interconnecting landing pad on the contact plug.